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LT1619 Low Voltage Current Mode PWM Controller
FEATURES
s s s s
DESCRIPTIO
s
s
s s
s s s
Wide VIN Range: 1.9V to 18V 300kHz Fixed Frequency Current Mode Control 1A Rail-to-Rail N-Channel MOSFET Driver Low 53mV Current Limit Threshold Voltage Improves Efficiency Implements Boost, SEPIC and Flyback Converters Requiring Low Side Power Transistors Internal Current Sense Amplifier with Leading Edge Blanking Up to 500kHz External Synchronization Burst Mode(R) Operation for High Efficiency at Light Load 140A Quiescent Current 15A Shutdown Current 8-Lead MSOP and SO Packages
The LT (R)1619 is a fixed frequency PWM controller for implementing current mode DC/DC converters with minimum external parts. The LT1619 operates with input voltages ranging from 1.9V to 18V and is suitable for a variety of battery-powered and distributed DC/DC converters. The internal rail-to-rail N-channel MOSFET driver operates either from the input in the nonbootstrapped mode or from the output in bootstrapped operation. The driver is designed to drive a low side power transistor in boost, SEPIC, flyback and other topologies. Converter efficiency is improved at heavy loads with a 53mV current sense voltage and at light load with Burst Mode operation. The operating frequency is internally set at 300kHz. The oscillator can also be synchronized externally up to 500kHz. No load quiescent current is 140A and shutdown current is 15A. The LT1619 is available in 8-lead MSOP and SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation.
APPLICATIO S
s s s
3.3V to 5V DC/DC Converters Distributed Power Supplies Isolated Power Supplies
TYPICAL APPLICATIO
VIN 3.3V
37.4k 12.4k
1 2 3
S/S FB VC GND
VIN DRV LT1619 GATE SENSE
8 7 6 5 0.1F
+
EFFICIENCY (%)
C1 22F 0.1F
L1 5.6H 5A VOUT 5V 2.2A
M1 Si9804
D1
75k 220pF 15nF
4
+
COUT 440F
RSENSE 0.01
1619 F01
C1: PANASONIC EEFCDOK220R COUT: KEMET T495X227K010AS (x2) D1: MBRD835L L1: COILCRAFT DO5022P-562
Figure 1. High Efficiency 3.3V to 5V DC/DC Converter
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Efficiency
95 90 85 80 75 70 1 10 100 LOAD CURRENT (mA) 1000
1619 F01a
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1
LT1619
ABSOLUTE
AXI U
RATI GS
Input Voltage (VIN) ................................... - 0.3V to 20V Gate Drive Supply Voltage (DRV) ............. - 0.3V to 20V Shutdown/Synch Voltage (S/S) ................ - 0.3V to 20V Feedback Voltage (FB) .............................................. VIN Compensation Voltage (VC) ...................................... 3V Gate Drive Output Current (GATE) ........................ 1.5A
PACKAGE/ORDER I FOR ATIO
TOP VIEW S/S FB VC GND 1 2 3 4 8 7 6 5 VIN DRV GATE SENSE
ORDER PART NUMBER LT1619EMS8
S/S 1 FB 2 VC 3
MS8 PACKAGE 8-LEAD PLASTIC MSOP
MS8 PART MARKING LTHC
TJMAX = 125C, JA = 200C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted.
PARAMETER Reference Voltage Reference Line Regulation FB Input Bias Current Error Amplifier Transconductance Error Amplifier Output Source Current Error Amplifier Output Sink Current Error Amplifier Clamp Voltage Undervoltage Lockout Threshold Input Voltage Range Switching Frequency Synchronization Frequency Range Maximum Duty Cycle Current Limit Threshold Burst Mode Operation Current Limit
q q q
CONDITIONS Measured at the FB Pin 1.9V VIN 18V VFB = VREF
q
VFB = 1V, VCOMP = 1V VFB = 1.5V, VCOMP = 1V VFB = 1V
1.9V VIN 18V
2
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U
W
WW U
W
(Note 1)
Current Sense Voltage (SENSE) ................. - 0.5V to VIN Operating Temperature Range (Note 2) .. - 40C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
TOP VIEW 8 7 6 5 VIN DRV GATE SENSE
ORDER PART NUMBER LT1619ES8
GND 4
S8 PART MARKING 1619
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 120C/ W
MIN 1.22
TYP 1.24 0.004 10
MAX 1.26 0.05 25 260 14 14 2.2 1.85 18
UNITS V %/V nA -1 A A V V V kHz kHz % mV mV
80 4 4 1.6 1.65 1.9 220 370 88 40
q
170 8.7 8.7
300 92 53 10
360 500 66
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LT1619
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted.
PARAMETER Current Sense Input Current Current Limit Delay Driver Output Rise Time Driver Output Fall Time Driver Output High Level Driver Output Low Level Shutdown Driver Output Level Idle Mode Driver Output Level S/S Pin Current Operating Supply Current Quiescent Supply Current Shutdown Supply Current Shutdown Threshold Shutdown Delay Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: The LT1619E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. CL = 3300pF CL = 3300pF IOUT = - 20mA IOUT = - 200mA IOUT = 20mA IOUT = 200mA VS/S = 0V, IOUT = 20mA VS/S = VIN, VFB = 1.5V, IOUT = 20mA VS/S = VIN VS/S = 0V VFB = 1V VS/S = VIN, VFB = 1.5V VS/S = 0V VS/S = 0V, VIN = 18V, TA = 85C 0.45 12 17
q
CONDITIONS VSENSE = 0V
q
MIN - 90
TYP - 120 150 30 35
MAX - 150
UNITS A ns ns ns V V
VDRV - 0.6 VDRV - 1.6
VDRV - 0.35 VDRV - 1.2 100 0.5 100 100 200 0.7 200 200 4 -2 9 140 15 40 220 19 1.2 33
mV V mV mV A A mA A A A V s
Note 3: TJ is calculated from the ambient temperature TA, the power dissipation PD and the thermal resistance JA of the package according to the formula: TJ = TA + PD * JA
TYPICAL PERFOR A CE CHARACTERISTICS
Bandgap Voltage vs Temperature
1.245 1.243 1.241
BANDGAP VOLTAGE (V)
VIN = 2.5V
1.239
IS/S (A)
1.237 1.235 1.233 1.231
2 1 0 -1
TA = 85C
S/S PIN CURRENT (A)
1.229 1.227 1.225 -40 -20 0 20 40 60 80 100 120
1619 G01
TEMPERATURE (C)
UW
IS/S vs VS/S
5 TA = -40C 4 3 TA = 25C 4 5
S/S Pin Current vs Temperature
VS/S = 2.5V 3 2 1 0 -1 -2 VS/S = 0V
-2 -3 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VS/S (V)
1619 G02
-3 -40 -20
0
20 40 60 80 TEMPERATURE (C)
100 120
1619 G03
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LT1619 TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Supply Current vs Input Voltage
45 IDLE MODE SUPPLY CURRENT (A) 40
SUPPLY CURRENT (A)
DEVIATION FROM NOMINAL FREQUENCY (%)
35 TA = -40C 30 TA = 25C 25 20 15 10 5 0 2 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V)
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TA = 85C
Maximum Duty Ratio vs Temperature
95 VIN = 2.5V 8 6 4 2 0 -2 -4
FREQUENCY DEVIATION (%)
94
CURRENT LIMIT THRESHOLD (mV)
DUTY RATIO (%)
93
92
91
90 -40
-20
40 20 0 60 TEMPERATURE (C)
Burst Mode Operation Current Limit Threshold vs Temperature
14
CURRENT LIMIT THRESHOLD (mV)
VIN = 2.5V 12 DUTY CYCLE = 0
SENSE PIN CURRENT (A)
SENSE PIN CURRENT (A)
10 8 6 4 2 0 -40 -20
40 20 60 0 TEMPERATURE (C)
4
UW
80
1619 G07
Idle Mode Supply Current vs Temperature
200 190 180 170 160 150 140 -40 -20 VIN = 2.5V
Frequency Deviation from Nominal vs Temperature
10 8 6 4 2 0 -2 -4 -6 -8 -10 - 40 - 20 0 60 40 20 TEMPERATURE (C) 80 100
1619 G06
VIN = 2.5V NOMINAL FREQUENCY = 300kHz
0
20 40 60 80 TEMPERATURE (C)
100 120
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Deviation from Nominal Frequency vs Input Voltage
TA = 25C NOMINAL FREQUENCY = 300kHZ 58 57 56 55 54 53 52 51
Current Limit Threshold vs Temperature
VIN = 2.5V
100
0
2
4
6 8 10 12 14 16 18 20 INPUT VOLTAGE (V)
1619 G08
50 -40 - 20
0
60 40 20 TEMPERATURE (C)
80
100
1619 G09
SENSE Pin Input Bias Current vs Temperature
-115 -117 -119 -121 -123 -125 -127 -129 -131 -133 VSENSE = 0V - 90 - 95 -100 -105 -110 -115 -120 -125 40 0 60 20 TEMPERATURE (C) 80 100
SENSE Pin Input Bias Current vs Sense Voltage
TA = 25C
80
100
-135 -40 -20
-130 -10
0
10
20
30
40
50
60
VSENSE (mV)
1619 G11 1619 G12
1619 G10
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LT1619
PI FU CTIO S
S/S (Pin 1): Shutdown and Synchronization. Shutdown is active low with a typical threshold voltage of 0.9V. For normal operation, the S/S pin is tied to VIN. To externally synchronize the controller, drive the S/S pin with pulses. FB (Pin 2): The inverting Input of the Error Amplifier. Connect the resistor divider tap here. Set VOUT according to VOUT = 1.24(1 + R1/R2). See Figure 1. VC (Pin 3): Compensation Pin for the Error Amplifier. VC is the output of the transconductance amplifier. Overall loop is compensated with an RC network from this pin to the ground. GND (Pin 4): Ground. Connect to local ground plane. SENSE (Pin 5): The Input of the Current Sense Amplifier. The SENSE pin is connected to the source of the N-channel MOSFET and to a sense resistor to the ground. The current limit threshold is internally set at 53mV, giving a maximum switch current of 53mV/RSENSE. GATE (Pin 6): The Output of the MOSFET Driver. DRV (Pin 7): The Pull-Up Supply of the MOSFET Driver. Tie this pin to VIN (Pin 8) for nonbootstrapped operation or to the converter output for bootstrapped operation. VIN (Pin 8): Supply or Battery Input. Must be closely bypassed to the ground plane.
BLOCK DIAGRA
VC 3
ERROR AMPLIFIER 1.24V
1.8V
+
gm
FB 2
-
VB
+
+
CLK CURRENT SENSE AMP
S/S 1
+
SHUTDOWN DELAY REF/BIAS CURRENT LIMIT COMPARATOR
-
ILIM
1619 F02
Figure 2. LT1619 Block Diagram
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RAMP COMP 300kHz SYNC OSCILLATOR
-
W
+
-
U
U
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VIN 8
-
A2
UVLO
+
-
A1 IDLE
+
VIN DRV 7
C1
S Q R
DRIVER
6
GATE LOAD RSENSE
5
SENSE
4 280ns LEADING EDGE BLANKING
GND
5
LT1619
OPERATIO
The LT1619 is a fixed frequency current mode switching regulator PWM controller that can be used in boost, SEPIC or flyback modes. The device operates from an input supply range of 1.9V to 18V, and has a separate supply pin (DRV) for the gate driver. The DRV pin can be bootstrapped to VOUT for additional gate enhancement in low voltage applications like 3.3V to 5V boost converters, or connected to the input supply for higher voltage inputs. To best understand operation of the LT1619, please refer to Figure 2, the Block Diagram. The gate drive circuit turns on the external MOSFET at the trailing edge of oscillator output signal CLK. MOSFET current is sensed with an external resistor (RSENSE of Figure 1). A leading edge blanking circuit disables the current sense amplifier for 280ns immediately following switch turn-on, preventing gate charging current from prematurely tripping the PWM comparator. A slope compensating ramp, derived from the oscillator, is added to the current sense output. The driver turns off the MOSFET when this sum exceeds the error amplifier output VC. The switch current is limited with a separate comparator. The compensating ramp is a progressive nonlinear function of the operating duty ratio whereas the current limit does not vary with the duty ratio. Error amplifier output VC determines the peak switch current required to regulate the output voltage. VC can be considered a measure of output current. At heavy loads, VC is in its upper range. Average and peak inductor currents are high. In this range, the inductor tends to run in continuous conduction mode (CCM), where current is always flowing in the inductor. As load current decreases, average and peak inductor current decreases. When the average inductor current falls below 1/2 of the peak-to-peak inductor current ripple, the converter enters discontinuous conduction mode (DCM), where current in the inductor reaches zero sometime during the discharge phase. Further reduction in output current moves VC towards its lower operating range, decreasing inductor current. Hysteretic comparator A1 determines if VC is too low for the LT1619 to operate efficiently. As VC falls below the trip voltage VB, A1's output goes high, turning off all blocks except the error amplifier, A1 and A2. The LT1619 enters the idle state and switching stops. The device draws just 140A from the input in the idle state. Output load current
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discharges the output capacitor, causing the output voltage to decrease. As VOUT decreases, VC increases. As VC increases above VB, switching action begins, delivering power to the output. The switch current sense threshold is about 10mV in this VC region. If the output load remains light, the output voltage will rise and VC will fall, causing the converter to idle again. This is known as Burst Mode operation. The burst frequency depends on input voltage, output voltage, inductance and output capacitance. Output voltage ripple during Burst Mode operation is usually higher than when the converter is switching continuously. Burst Mode operation increases light load efficiency because it delivers more energy per clock cycle than possible with discontinuous mode operation and extremely low peak switch current, allowing fewer switching cycles to maintain a given output. IC supply current therefore becomes a small fraction of the total input current. Setting Output Voltage The output voltage of the LT1619 is set with resistive divider R1 and R2 connected from the output to ground as detailed in Figure 3. The divider tap is tied to the device FB pin. Current through R2 should be significantly higher than the FB pin bias current of 25nA. With R2 = 10k, the input bias current of the error amplifier is 0.02% of the current in R2.
VO R1 VO = 1.24V 1 + R1 R2 VO -1 R1 = R2 1.24 LT1619 FB R2
() ()
1619 F03
Figure 3. Feedback Resistive Divider
Synchronization and Shutdown The S/S pin (Pin 1) can be used to synchronize the oscillator to an external source. The S/S pin is tied to the input (VIN > 1.9V) for normal operation. The oscillator in the LT1619 can be externally synchronized by driving the S/S pin with a pulse train with an amplitude of at least 1V. The maximum allowable rise time is a function of the pulse amplitude, as shown in Table 1. Rise times equal to
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LT1619
OPERATIO
or less than the number specified in Table 1 are acceptable. The maximum duty cycle is essentially unaffected by synchronization. The device will go into shutdown mode if the S/S pin voltage stays below the shutdown threshold of 0.45V for
Table 1. Maximum Allowable Rise Time of Synchronization Pulse. Rise Time Can Be Slower if Clock Amplitude is Higher
SYNCHRONIZATION AMPLITUDE (V) 1.2 1.5 2.0 2.5 3.0 MAXIMUM ALLOWABLE RISE TIME (ns) 120 220 350 470 530
APPLICATIO S I FOR ATIO
Inductor
The value of the inductor is usually selected so that the peak-to-peak ripple current is less than 30% of the maximum inductor current. The inductor should be able to handle the maximum inductor current at full load without saturation. Powder iron cores are not suitable for high frequency switch mode power supply applications because of their high core losses. Ferrite cores have very low core losses and are the material of choice for high frequency DC/DC converters. Power MOSFET Driver The LT1619 is capable of driving a low side N-channel power MOSFET with up to 60nC of total gate charge (Qg). An external driver is recommended for MOSFETs with greater than 80nC of total gate charge. The peak gate drive current varies from 0.5A with VDRV = 2.5V to 1.2A with VDRV = 10V. The MOSFET driver is capable of charging the gate of the power MOSFET to within 350mV of the upper gate drive supply rail (DRV). It can also pull the gate of the MOSFET to within 100mV of ground during turnoff. The upper supply rail of the gate drive is brought out as a device
VIN DRV LT1619 GND RS
+
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more than 33s. This shutdown delay is reset whenever the S/S pin voltage rises above the shutdown threshold. Applying a logic low signal at the S/S pin causes the gate drive output to go low. Although all circuits in the LT1619 are disabled, the pull-down circuit in the MOSFET buffer is still biased on. It is capable of shunting any leakage or transient current at the GATE pin to ground, eliminating the need for an external bleed resistor. The LT1619 consumes 15A in shutdown. The LT1619 is guaranteed to start with a minimum VIN of 1.85V. Comparator A2 senses the input voltage and generates an undervoltage lockout (UVLO) signal if VIN falls below this minimum. While in undervoltage lockout, VC is pulled low and the LT1619 stops switching. The supply current drawn by the device falls to 140A. pin (DRV) for design flexibility. In a boost converter design, the DRV pin can be tied to the converter output if the minimum input voltage is insufficient to fully enhance the power MOSFET. During start-up, the MOSFET is driven with a gate voltage starting from VIN - VD (VD is the forward voltage of the rectifying diode). As the output voltage rises, the gate drive also increases until steady state is reached. If the steady-state converter output voltage exceeds the maximum allowable gate source voltage and the input voltage is sufficient to enhance the MOSFET, the DRV pin is tied to the input supply. For a SEPIC converter, the DRV pin can be tied to the input or diode OR'ed from the input and the output (Figure 4).
*
VOUT
+ *
1619 F03
Figure 4. SEPIC Converter with Diode OR'ed Gate Drive Supply
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LT1619
APPLICATIO S I FOR ATIO
Power MOSFET MOSFET power dissipation can be separated into frequency independent and frequency dependent components. The RDS(ON) loss in the switch is the product of the mean square switch current and switch RDS(ON) and it does not vary with the operating frequency. The frequency-dependent switching losses consist of 1) switch transition loss due to finite rise and fall times of the drain source voltage and the drain current 2) gate switching loss, i.e., a packet of charge Qg (the total gate charge) which is moved from the gate drive power supply to ground in every switch cycle, and 3) the drain switching loss, charge stored on the parasitic drain capacitance, COSS is dumped to ground as the switch is turned on. The transistor loss can be expressed as: PLOSS = IDRMS2 RDS(ON) + transition loss + QgVGfS + 1/2COSSVDS(OFF)2fS where the transition loss can be estimated with:
2
Transition Loss = ID
CRSSVDS(OFF) fS IG(AVG)
Qg = The total gate charge VG = Gate drive voltage VDRV IG(AVG) = The average MOSFET buffer output current fS = Operating frequency CRSS = The average CGD between VDS = 0V and VDS = VDS(OFF) At low VDS(OFF) (12V) and operating frequencies below 500kHz, the ohmic losses often dominate. For high voltage converters, the transition loss and COSS charge dumping loss can dramatically impact the converter efficiency. MOSFETs with lower parasitic capacitances but higher RDS(ON) may actually provide better efficiency in these situations. Capacitors In a switch mode DC/DC converter, output ripple voltage is the product of the equivalent series resistance (ESR) of
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the output capacitor and the peak-to-peak capacitor current. Depending on topology, current feeding the output capacitor can be continuous or discontinuous. The input current can also be continuous or discontinuous even if the inductor current itself is continuous. In boost topology, the inductor is in series with the input source so the input current is continuous and the output current is discontinuous. In buck-boost or flyback converters, the inductor is not in series with the input source nor the output, so neither the input current nor output current is continuous. Whenever a terminal current is discontinuous, the capacitor at that terminal should be chosen to handle the ripple current. Capacitor reliability will be adversely affected if the ripple current exceeds the maximum allowable ratings. This maximum rating is specified as the RMS ripple current. Several capacitors may be mounted in parallel to meet the size and ripple current requirements. Besides the ripple voltage requirements, the output capacitor also needs to be sized for acceptable output voltage variation under load transients. Current Sensing Resistor RSENSE The LT1619 drives a low side N-channel MOSFET switch. The switch current is sensed with an external resistor RSENSE connected between the source of the MOSFET and ground. The internal blanking circuit blocks the voltage spike developed across RSENSE for 280ns at switch turnon. The switch is turned off when the instantaneous voltage across RSENSE exceeds the current limit threshold, VSENSE. Allowing variations in VSENSE yields:
RSENSE = VSENSE(MIN) IL(MAX)
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The current limit threshold is constant and does not vary with duty ratio. Due to low signal level of the sense voltage, low inductance sense resistors are required to reduce switching noise. Low TC resistors maintain constant current limit over temperature. Dale WSL and IRC series sense resistors meet these criteria.
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LT1619
APPLICATIO S I FOR ATIO
Diode Schottky diodes are recommended for low output voltage applications because of their low forward voltage. Since Schottky diodes have negligible stored charge, charge dumping loss is also reduced. The reverse breakdown voltage of the diode should exceed the maximum reverse voltage stress of the topology used. The diode should also be able to carry the peak diode current with acceptable foward voltage. For the boost converter in Figure 1, the peak inductor current is approximately 5A. A Motorola MBRD835 is used due to its low forward voltage. Lowering Burst Mode Operation Current Limit The LT1619 automatically enters Burst Mode operation as VC voltage falls below VB. The corresponding switch current is the Burst Mode operation switch current threshold, ID(BURST). The effective Burst Mode operation current threshold can be lowered by adding an offset to the input of the current sense amplifier so that the switch current appears higher to the PWM comparator. This has the effect of shifting the VC operating range above VB. Although Burst Mode operation is not entirely disabled, the peak switch current before entering Burst Mode operation is greatly reduced due to the offset of the current sense amplifier. The peak switch current is also determined by the current sense amplifier blanking. To lower the Burst Mode operation current sense threshold, a resistor ROS is added between the SENSE pin and the sense resistor RSENSE (Figure 5). The input bias current IBIAS of the current sense amplifier, which has a
CURRENT SENSE AMPLIFIER
ID
IBIAS = 120A
IBIAS = 120A 5 SENSE 4 GND ROS
RSENSE
1619 F05
Figure 5. Lowering Burst Mode Operation Current Limit
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tolerance of 25% and is temperature stable, develops an offset voltage at the sense input. The value of ROS required for non-Burst Mode operation can be obtained with the expression: IBIASROS VSENSE(BURST) where VSENSE(BURST) = (Burst Mode operation peak switch current, ID(BURST)) * RSENSE For example, if IBIAS = 120A and VSENSE(BURST) = 10mV:
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ROS
10mV = 83 120A
Allowing for 25% and 30% variations in IBAIS and VSENSE(BURST) respectively: ROS = (1.25)(1.3)(83) Choose ROS = 137 to completely disable Burst Mode operation. Lower values of ROS (for example, 50 to 100) can be used to lower the effective Burst Mode current limit. The value of the sense resistor is then adjusted to compensate for the reduced full-scale sense voltage. IBIASROS + IL(MAX)RSENSE = 40mV Filtering Current Sense Signal In a current mode converter, the current sense circuit senses the switch current and terminates the switch conduction. In the LT1619, the current sense amplifier has a full-scale input voltage range from the ground to the current limit threshold (53mV). Due to high speed switching transients and parasitic trace inductances, the current sense signal VSENSE tends to be noisy. If the VSENSE switching transient is excessive, the current sense amplifier will amplify the spurious transient instead, resulting in jittery operation. In situations where the internal leading edge blanking is inadequate, a lowpass filter (Figure 6) with corner frequency about 5 times the switching frequency can be used to further attenuate high speed switching transients. In Figure 6 the lowpass filter ROS and CS has a corner frequency of:
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LT1619
APPLICATIO S I FOR ATIO
fCORNER = 1 5fS 2ROSCS
(The input impedance of the sense amplifier at the SENSE pin is 2500 and ROS is typically less than 137.) Typical values for ROS and CS are 100 and 1nF. The 100 value for ROS reduces Burst Mode threshold; use 10 and 10nF when this is not desireable.
LT1619 PWM COMPARATOR CURRENT SENSE AMPLIFIER
+ -
5
SENSE
ROS
CS RSENSE 4 GND
Figure 6. Current Sense Filter for Improving Jitter Performance
Use of Shutdown Function to Modify Undervoltage Lockout The LT1619 is designed to operate from an input supply with voltage as low as 1.85V. Shutdown is activated when the S/S pin is pulled below 0.45V. The shutdown threshold is slightly greater than one junction diode forward voltage and has the temperature characteristics of a junction diode. The S/S pin is normally tied to the input when operating from a low voltage input source. Consider the 12V to - 65V isolated flyback converter (see Typical Applications). The converter draws 3A at low line while delivering 0.4A to the output. If the S/S pin is tied to the input, then the LT1619 will start switching as soon as VIN exceeds the internal UVLO threshold. With full load, the converter can draw much higher than the steady-state 3A from the input source during start-up. If the input source is current limited, the input voltage will collapse and latch low. The start-up problem can be prevented by adding a zener diode and a resistor to the S/S pin (Figure 7). This is equivalent to increasing undervoltage lockout voltage of the controller. Before VIN exceeds the zener voltage VZ, the S/S pin current is shunted to the ground through the
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VIN VZ IS/S R3 1 2 3 4 S/S FB VC GND VIN DRV LT1619 GATE SENSE
1619 F07
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8 7 6 5
(
IS/S VS/S = 0
)
R3 < SHUTDOWN THRESHOLD
UVLO THRESHOLD = VZ + SHUTDOWN THRESHOLD VZ + VBE IS/S -2A VS/S = 0
Figure 7. Implementing Undervoltage Lockout
ID
I
+ -
VSENSE
I
+ -
V
ZENER DIODE
AVALANCHE DIODE
1619 F06
V 0 BV < 5V
Figure 8. I-V Characteristics of Zener and Avalanche Breakdown Diodes
VIN
R4 1 2 C1 R3 3 4 S/S FB VC GND VIN DRV LT1619 GATE SENSE
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8 7 6 5
Figure 9. Filtering Input Voltage Ripple in UVLO Circuit
resistor R3. The voltage developed across R3 due to IS/S should be less than the shutdown threshold. The LT1619 remains off until VIN exceeds the sum of VZ and the shutdown threshold. True zener diodes (BV < 5V) and higher voltage avalanche diodes have different I-V characteristics (Figure 8). They need to be biased appropriately (value of R3) in order to obtain correct UVLO threshold. When implementing UVLO with converters with high input ripple voltages (such as flyback and forward), the circuit in Figure 7 is modified and shown in Figure 9.
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LT1619
APPLICATIO S I FOR ATIO
Here the input voltage ripple is filtered with R3, R4 and C1 so as to prevent the input ripple from falsely tripping the LT1619 synchronization circuit. It is recommended that:
1 R4 R3 5 1
and
2 R3 || R4 C1
(
)
<< fOSC
Implementation of Hysteretic UVLO with External Synchronization The UVLO circuit shown in Figure 10 operates down to 0.9V supply voltage. Algebraically the UVLO trip points are:
R5 VINH = VZ + VBE 1 + R6 || R7 and VINL = R5 || R6 || R7 + R9 R5 R5 UVLO Hysteresis = VINH - VINL = VZ + R5 + R7 + R9 R5 || R7 + R9 R5 VBE - R6 || R7 R6 R5 || R7 + R9 R5 || R7 + R9
(
) VZ + VBE
(
(
(
VIN R8 30k 8.2V R9 510k R7 51k CLK D1 BAT85 3 R5 51k Q1 2N2222 R6 51k Q2 2N2222 4 1 2 S/S FB VC GND VIN DRV LT1619 GATE SENSE
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+ -
VIN UPPER TRIP POINT = 10V VIN LOWER TRIP POINT = 8.4V
Figure 10. Addition of Hysteresis UVLO While Synchronizing the LT1619. Component Values Shown are for the Upper and the Lower VIN Trip Points of 10V and 8.4V. In UVLO, the Gate Drive is Disabled by Pulling the VC Pin Low. Disabling the Clock Shuts Down the LT1619. If Not Synchronized, the Collector of Q2 Can Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated
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The collector votage of Q2 is made about 1.4V at the VIN lower trip voltage. This is necessary to prevent the UVLO circuit from interfering with the feedback amplifier in the LT1619. Trickle Current Start from High Voltage Supplies The low shutdown and idle mode quiescent supply currents of the LT1619 can be utilized to implement trickle current start from high voltage input sources (such as a 36V to 72V telecom bus). The trickle current start-up circuit in Figure 11 is modified from the UVLO circuit of Figure 10. R10 is a high value resistor that charges the storage capacitor C2 during start-up. Before VCC reaches the upper UVLO trip point, Q2 holds the S/S pin low. The LT1619 draws shutdown mode current (15A) from VCC. Q2 collector can also be tied to the VC pin through a diode as in Figure 10. The LT1619 will then draw idle mode quiescent current (140A) from VCC. R10 should be able to charge C2 while supplying current to the UVLO circuit and the LT1619. Maximizing R5 to R9 values reduces power dissipation in R10. When VCC crosses the upper UVLO threshold, the LT1619 starts switching and its current consumption increases. Before the bootstrap takes over, the LT1619 draws its current from C2. VCC ramps towards the lower UVLO threshold. Increasing the value of C2 allows more time for the bootstrap circuit to establish itself before the converter enters undervoltage lockout.
HV VIN 8 7 C2 6 R7 5 3 R5 Q1 R6 Q2 4 VC GND 2 FB R8 R9 1 S/S VIN DRV LT1619 GATE SENSE
1619 F11
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)
)
)
R10 VCC 8 7 D2
BOOTSTRAP WINDING
T1 6 5
Figure 11. Trickle Current Start-Up with Bootstrapped VCC
1619fa
11
LT1619
APPLICATIO S I FOR ATIO
Increasing Ramp Compensation While Synchronizing The LT1619 is synchronized by forced discharge of the internal timing ramp. The timing ramp amplitude decreases as the synchronization frequency increases. Since the internal compensation ramp is derived from the timing ramp, reduced timing ramp results in diminished compensating ramp. If the LT1619 is synchronized at frequencies 20% to 30% higher than the free-running frequency, external ramp compensation will be required. Figures 12 and 13 show two such schemes. In both figures the compensating ramps are kept linear by making R11-C1 and R14-C2 products substantially higher than the synchronizing period. The compensation ramps,
CLK 1 2 3 4 S/S FB VC GND VIN DRV LT1619 GATE SENSE 8 7 6 5 C1 220pF R11 100k D2 1N4148 MAIN POWER TRANSISTOR Q1 2N2222 R12 2200 R13 51
RSENSE
1619 F12
Figure 12. Increasing Ramp Compensation. Q1 Buffers the C1 Ramp. D2 Discharges C1. Values Shown are for 10V Gate Drive and 15mV Ramp Across R13 at 90% Duty Cycle and 500kHz
CLK
1 2 3 4
S/S FB VC GND
VIN DRV LT1619 GATE SENSE
8 7 6 5 C2 2.2nF D2 1N4148 R14 8200 D3 1N4148 R15 2400 R13 51 RSENSE
1619 F13
Figure 13. Externally Increasing Ramp Compensation. Similar to Figure 12 Except That C2 is Not Buffered with Transistor
12
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whose peak amplitudes are made between 1/4 to 1/3 of the current limit threshold, are developed across R13. As a result, the effective current limit threshold is reduced by the sum of the compensating ramp and the offset voltage developed across R13 due to the SENSE pin input bias current (see Figure 5). Moreover, the current limit threshold becomes duty cycle dependent. PC Board Layout and Other Practical Considerations The following is recommended for PC board layout: 1. Trace lengths of the branches carrying switched current should be kept short. For example, in the boost converter of Figure 1, the circuit loop formed by M1, RSENSE, D1 and COUT carries switched current. The size of this loop must be minimized. RSENSE and COUT should be grounded to a single point on a large ground plane. This reduces switching noise and overall converter jitter. It is also preferable to ground the input capacitor C1 close to the common point between COUT and RSENSE although this is less important. 2. Keep the trace between the sense resistor and the SENSE pin short. When sensing high switch current, Kelvin connection to RSENSE is necessary. 3. Bypass both the VIN and DRV pins with ceramic capacitors next to the IC and the ground plane. 4. Keep high voltage switching nodes, such as the drain and gate of the MOSFET, away from the FB and VC pins. 5. Use inductor so that its ripple current is between 1/4 and 1/3 of its peak current. Steeper inductor current ramp results in sharper PWM comparator switching, hence less jitter. 6. In most cases, filtering the current sense signal is not necessary for jitter-free operation. Figure 14 is the PC board layout for the 5V/8A and 12V/5A boost converters shown in Figures 15a and 16a.
1619fa
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LT1619
APPLICATIO S I FOR ATIO
R1 RC 1 2 LT1619 R2 CZ CP 3 4 6 5 D RSENSE CIN1 GND COUT1, 2 D1 D G 8 7 S M1 G S M1
Figure 14. Recommended Component Placement for the Boost Converters in Figures 15a and 16a
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CDRV CIN2 VOUT L1 VIN
1619 F14
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13
LT1619
APPLICATIO S I FOR ATIO U
VIN 3.3V 1 2 3 CP 150pF RC 75k CZ 15nF 4 S/S FB VC GND VIN DRV LT1619 GATE SENSE 8 7 6 5 CIN2 1F CERAMIC CDRV 0.1F CERAMIC L1 1H
CIN1: SANYO POSCAP 6TPB150M x2 COUT1: SANYO POSCAP 10TPB220M x4 D1: MOTOROLA MBRB1545CT L1: SUMIDA CEPH149-1R0 RSENSE: PANASONIC 0.002 1W
EFFICIENCY (%)
14
W
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+
CIN1 300F
M1 D1 FDS6680A x2 COUT1 RSENSE 220F x4
5V 8A
+
COUT2 10F CERAMIC
R1 37400 R2 12400
1619 F15a
Figure 15a. 3.3V to 5V/8A Boost Converter
89 88 87 86 85 84
VIN = 3.3V
83 0.01
0.1 1 LOAD CURRENT (A)
10
1619 F15b
Figure 15b. Efficiency of the 5V/8A Boost Converter
1619fa
LT1619
APPLICATIO S I FOR ATIO
1 2 3 CP 47pF RC 68.1k CZ 2200pF 4
S/S FB VC GND
VIN DRV LT1619 GATE SENSE
8 7 6 5
CIN1: SANYO OS-CON 10SA100M COUT1: SANYO OS-CON 16SA150M x4 D1: MOTOROLA MBRB1545CT L1: SUMIDA CDEP149-1R8 RSENSE: PANASONIC 0.002 1W
Figure 16a. 5V to 12V/5A Boost Converter
95 94 93
VIN = 5V
EFFICIENCY (%)
92 91 90 89 88 87 86 85 0.01 0.1 1 LOAD CURRENT (A) 10
1619 F16b
Figure 16b. Efficiency of the 12V/5A Boost Converter
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VIN 5V CIN2 1F CERAMIC CDRV 0.1F CERAMIC L1 1.8H
W
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+
CIN1 100F
M1 D1 FDS6690A x2 COUT1 RSENSE 600F
12V 5A
+
COUT2 10F CERAMIC
R1 107k R2 12400
1619 F15a
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LT1619
TYPICAL APPLICATIO S
VIN 4.75V TO 5.25V T1
*
1F
+
*
1 1.1k 2 3 2.2nF 36k 22nF 4 S/S FB VC GND VIN DRV LT1619 GATE SENSE 8 7 6 5 0.007 2N5210 432k 1%
1619 F17a
4.7F FILM
MBRS340T3
10F
SUD45N05-20L 50V, 0.018 43nC
30
220pF 2N5210 10.5k 1%
T1: COILTRONICS CTX02-14261, EFD20-3F3, 6 WINDINGS EACH, 12H
Figure 17a. 5V to - 48V Cuk Converter
90 89 88 87
EFFICIENCY (%)
VIN = 5.25V
86 85 84 83 82 81 80 79 10
VIN = 5V VIN = 4.75V
100 LOAD CURRENT (mA)
1000
1619 F17b
Figure 17b. Efficiency of the 5V to - 48V Cuk
16
+
1500F 6.3V SANYO MV-GX
1N749 4.3V
*
15
*
4.7F FILM
+
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* *
MBRS340T3
-48V/0.5A
470F 35V SANYO MV-GX
470F 35V SANYO MV-GX
1M
12k
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LT1619
TYPICAL APPLICATIO S
VIN 10.5V TO 13.7V
8.1V
0.22F 50V
1k 1W
20k
MBRS1100T3
1 0.1F 82k 2 3 100 1F 4
S/S FB VC GND
VIN DRV LT1619 GATE SENSE
10k 150F 20V SANYO 20SV150M (OS-CON)
Figure 18a. Isolated Local SLIC Power Supply (Flyback) 20W Total Output Power (65V/0.3A or 32.5V/0.6A)
EFFICIENCY (%)
Figure 18b. Efficiency of the Isolated Local SLIC (Flyback)
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8 7 6 5
10k
CNY17-3 6.2V 220pF
T1
*
43 W1 W3
330pF 100V 43 1/4W
2.2F 40V 62k
100 470pF -32.5V
470
*
MBRS1100T3
121
*
330pF W4 50V
W2
1F 50V
2.2F 40V
2.49k -65V
LT1431 1 8 COLL REF 2 7 NC NC 3 6 V+ FGND 4 5 NC SGND
*
MBRS1100T3
10F
IRLR024N 55V, 0.065 QG = 15nC
T1 PHILIPS EFD20-3F3-A100-S CORE SET (0.013" GAP, AI = 100nH/T2 W4 6T TRIFILAR 28AWG W3 24T 28AWG W2 24T 28AWG W1 6T TRIFILAR 28AWG 2mil POLYESTER FILM
0.008
1619 F18a
90 85 80 75 70 65 60 55 50 10 100 LOAD CURRENT (mA) 1000
1619 F18b
VIN = 13.7V VIN = 12V VIN = 10.5V
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17
LT1619
PACKAGE DESCRIPTION
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
5.23 (.206) MIN
0.42 0.04 (.0165 .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT DETAIL "A" 0 - 6 TYP 4.90 0.15 (1.93 .006) 3.00 0.102 (.118 .004) NOTE 4
0.254 (.010) GAUGE PLANE
0.18 (.077) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.13 0.076 (.005 .003)
MSOP (MS8) 0802
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
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0.889 0.127 (.035 .005)
3.2 - 3.45 (.126 - .136)
0.65 (.0256) BSC
3.00 0.102 (.118 .004) (NOTE 3)
8
7 65
0.52 (.206) REF
0.53 0.015 (.021 .006) DETAIL "A"
1 1.10 (.043) MAX
23
4 0.86 (.034) REF
0.65 (.0256) BSC
1619fa
LT1619
PACKAGE DESCRIPTION
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.050 BSC 8 N N .245 MIN .160 .005 .228 - .244 (5.791 - 6.197) 1 .030 .005 TYP 2 3 N/2
RECOMMENDED SOLDER PAD LAYOUT
.010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) 0- 8 TYP
.016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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.045 .005
.189 - .197 (4.801 - 5.004) NOTE 3 7 6 5
.150 - .157 (3.810 - 3.988) NOTE 3 N/2
1
2
3
4
.053 - .069 (1.346 - 1.752)
.004 - .010 (0.101 - 0.254)
.014 - .019 (0.355 - 0.483) TYP
.050 (1.270) BSC
SO8 0502
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19
LT1619
TYPICAL APPLICATIO
VIN 4V TO 28V C4 1.5F 100V
D4 1N4687 4.3V LOW LEVEL (IZT = 50A)
C4, C5: VITRAMON VJ1825Y155MXB (1825/X7R) C6: TAIYO YUDEN LMK325BJ106MN (1210/X7R) C8: TAIYO YUDEN EMK316BJ105ML (1206/X7R) T1: COILTRONICS VP1-0190 (ER11/5, 6 WINDINGS EACH 12.2H)
Figure 19. 2.5W, 4VIN-28VIN to 5V/0.5A Nonisolated Supply
RELATED PARTS
PART NUMBER LT1370 LT1372 LT1613 LTC1624 LT1680 LT1698 LTC1871 LTC1872 LT1946 LT3710/LT3781 DESCRIPTION 500kHz, 6A Switching Regulator 500kHz, 1.5A Switching Regulator 1.4MHz, SOT-23 DC/DC Converter Switching Regulator Controller Synchronous Boost Controller Isolated or Nonisolated 10W to 100W Power Supply Solution with Multiple Outputs No RSENSE Boost, Flyback, SEPIC Controller SOT-23 Boost Controller 1.2MHz, 65A DC/DC Converter Isolated or Nonisolated 10W to 100W Power Supply Solution with Multiple Outputs COMMENTS Boost, Buck, Flyback, Forward, Inverting; 42V Switch Voltage SO-8, 2.7V VIN 30V, 42V Switch Voltage Fixed Frequency, 0.9V VIN 10V, 36V Switch Voltage SO-8, Drives N-Ch MOSFET, 3.5V VIN 36V Synchronous Operation for High Current/High Efficiency 50% Lower Cost than Quarter Brick and Half Brick Modules Fits the Foot Print 2.5V VIN 36V, Current Mode Control, 50kHz to 1MHz Adjustabe Frequency, MSOP-10 550kHz Fixed Frequency, Current Mode MSOP-8, 5V to 12V/400mA 50% Lower Cost than Quarter Brick and Half Brick Modules Fits the Foot Print
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
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7 10 * 2 5* 3 6* C5 1.5F 100V Q1 FMMT3904 8 7 D3 MBRS0530T1 6 5 R7 30 Q3 MMFT3055VL R6 3.74k 1% R5 100 C1 0.022F T1 9 R3 5.6k
* 12
1
*4
8
* 11
D2 MBRS340T3
VOUT 5V 0.5A
VIN DRV GATE
SENSE LT1619 2 FB S/S GND 1 C8 1F 16V 4 VC 3 R9 2.2k C9 2.2nF C7 220pF R8 0.015
C6 10F 10V
R10 1.24k 1%
1619 TA01
1619fa LT/TP 1002 1K REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2000

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